We provide solutions for low-power ASIC implementation from specification to prototype (S2P) development for different applications and implementation of algorithms and H/W realization with co-simulation. The internal process is developed to perform synthesizable RTL design, design, and verification to reach more than 90% code coverage as a release benchmark, developing RTL synthesis environment with constraints from the specification and releasing GDSII with industry standard physical design flow.
Analog peripheral blocks are also designed and characterized to meet the interface standard which comprises the different types of simulations across PVT with parametric options and Monte-Carlo.
The FPGA team drives the system level validation using IP integration flow. The leadership team is having a strong understanding of interface IPs at peripherals and supports in timing fixing for the customer problems. We have worked with XILINX ultra-scale series for AI applications. Optimization at synthesis and implementation stages to achieve better utilization factor, modifying RTL to utilize URAM and BRAM blocks and implementing algorithms to optimize the time critical paths using HLS are some of our strengths and achieved milestones with past customer projects.
VLSIPRO has strong capabilities to provide advisory to complete EDA platform set-up solutions, Process Design Kit (PDK) enable program to work with different foundries like UMC, TSMC, XFAB etc. to enable the start-ups with end-to-end semiconductor flow (CAD-Foundry-Prototyping). We are the experts to complete the technology survey for selecting the appropriate devices and IPs availability and selecting the go-to PDKs to meet your specification requirements.
